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I just got Jeri Ellsworth’s web video shows on my radar, namely The Fat Man and Circuit Girl. She and co-host George Sanger do an awesome job of explaining electrical engineering, science concepts, and various forms of hackery in a clear, straightforward, and fun way.

Jer’s just started experimenting with short videos, with limited editing, of her describing something that’s caught her interest, like a video lab journal. This vid, Short Circuit #1, is her describing how an analog falling edge detector circuit works (and yes, she knows that she said “variable capacitor” when she meant “variable resistor”).

BTW: Jeri will be at Maker Faire in May! She’ll be showing off her Easy Bake Oven chip lab.

Fat Man and Circuit Girl

Gareth Branwyn

Gareth Branwyn is a freelancer writer and the former Editorial Director of Maker Media. He is the author or editor of a dozen books on technology, DIY, and geek culture, including the first book about the web (Mosaic Quick Tour) and the Absolute Beginner’s Guide to Building Robots. He is currently working on a best-of collection of his writing, called Borg Like Me.


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Comments

  1. Jason says:

    Nice to see Jeri still making headlines. I first met her at a Commodore 8-bit meeting, she wowed everyone with her homemade video card.

  2. dave says:

    Any ideas why people think that logic gates are analog? Several other bits were incorrect in this video, but it was interesting anyway.

  3. Gary says:

    People think logic gates are analog because they actually ARE analog. I don’t mean to shake the foundation of anyone’s beliefs by pointing that out. All digital logic has finite rise times, slew rates, propagation delays, input/output impedances, and many other qualities which are not apparent at low frequencies. But they are most certainly there, and will bite you in the butt as you start pushing the frequency limits any logic gate was designed for. That’s when they start showing their non-ideal real-world qualities, and their behavior is often unwanted. In the case of the first schematic of the edge detector, Jeri was showing that the delay through three inverters is a very real effect, and this produced the desired output of catching a rising signal. The length of the output pulse could be extended by either slowing down the inverter circuit (with an R/C tossed in there) or by adding more gates.

    Take a look at the data sheet for any logic chip and you will see things like gate delays and the analog values that the chips consider high/low – both for inputs and outputs. For a 5v logic chip, you won’t find values that say exactly 0v and 5v. They are always in between. For example, anything below 0.7v might be considered low, and anything above 4.3v might be considered high. It just depends on the technology, like CMOS or TTL.

    The only error I saw in the video was the resistor/cap slip explained in the post. Everything else makes perfect sense.