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Fig03
EiED online’s Bill Wong reviews the propellor multicore processor from Parallax (best known for their BASIC stamp) – “Parallax took a major turn from its bread and butter Basic Stamps and SX processors with its new Propeller architecture. The Propeller packs eight 32-bit processors, called cogs, into a single package… Packing eight identical processors in the same package with shared memory may seem like a straight forward architecture but the Propeller is a bit more complicated and novel. For example, all eight cogs have access to all of the same 32 IO pins at the same time. This can make debugging a bit difficult if two processors accidentally use the same pin at the same time in a different fashion. This simply means designers need to have a good understanding of the application and its implementation.” [via] – Link.

Related:

  • First look at Parallax’s Propeller chip – Link.
  • Parallax – Link.
  • Propeller – Link.

Phillip Torrone

Editor at large – Make magazine. Creative director – Adafruit Industries, contributing editor – Popular Science. Previously: Founded – Hack-a-Day, how-to editor – Engadget, Director of product development – Fallon Worldwide, Technology Director – Braincraft.


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Comments

  1. lwatcdr says:

    I took a look at it and thought wow that is so cool. Then I thought what would I ever use it for. All those cogs and so little ram. I for the life of me can not think of any really good applications for it.
    What applications did Parallax have in mind for it?

  2. Stokes says:

    I’d guess agent-based AI, a la The Society of Mind. Anyway, the cogs could access external memory via the i/o pins, couldn’t they?

  3. lwatcdr says:

    the cogs could access external memory via the i/o pins, couldn’t they?
    Well there are only 32 bits of IO. I think you could hang memory off of it but it would be a real kluge to say the least.
    It would be a very limited AI system to say the least. How would you write it. What kind of IO would you use? Like I said I would love to see some application notes for this thing. I would love a nice multicore CPU but this one seems so limited. I haven’t found anything on how they handle resource management and deadlock prevention.
    If they don’t handle that then programing it effectively will be all sorts of fun.
    It might have some us in robotics but again putting all that work into it without having specific problem to solve seems less than bright.
    I asked a fellow programmer what he thought of it and he came up with the same answer I did. It looks really cool but I have no idea what I would use it for.
    With more memory I could imagine using it for engine management, anti-lock breaks, maybe network routing. That tiny address space is just too small each cog only has 512 words of memory the main system only has 8k words of ram and 8k words of ROM. Is it ROM or flash. If it is ROM I would bet that they use that to store the spin system. So if you don’t use Spin that is wasted space.
    Put in a tiny TCP/IP stack and you are down to less than 5k words. It seems very cool but what would you use it for keeps popping into my head.

  4. ubi-randomtype says:

    I got one a while ago, as I was placing an order for a few things I decided to throw that in too.
    haven’t had the time to even assemble the thing, but I’m intrigued by its capabilities.
    I’ll try giving it a shot in the future, maybe I’ll just never use it.

  5. Stokes says:

    What kind of AI? Myself, I’d probably implement something biomimetic, taking ideas from Minsky’s ‘society of agents’ model and Braitenberg’s “Vehicles”. Several cogs would be devoted to stimulus/response behavior, the others would form a hierarchy that processed information received from lower levels and pass it onto higher ones. I’d also probably not have the Propeller itself do the bulk of the sensing work; there are special-purpose chips that can do most of the processing, but at the cost of using i/o lines.

    Anyway, I think people underestimate what you could do with 8K words of RAM. For example, you can implement a TCP/IP stack in far fewer than 3K words… how about 256 bytes?

  6. figgalicous says:

    Seems like you could use this for something like This

  7. Oracle1729 says:

    Iwatcher, you grossly underestimate the power of these chips. I’m guessing from the fact that you want a “nice multicore CPU” that you come from a GUI RAD programming background. To an embedded designer, the specs here are great.

  8. lwatcdr says:

    Actually I am doing embedded development. It is on an Xscale using Linux as the OS so I am sort of on the middle ground between a full PC and PICs, AVRs, and 8051s.
    You see that is where I am confused. All those cores and so little memory just sort of boggles my mind.
    Seems like overkill for most embedded devices but not enough memory for things that could use the multiple cores.
    The development system offers VGA out and a keyboard so that makes me think of GUI like applications.
    I could see using a core or two to generate a graphics display, a core for audio, and then use the rest of the cores for doing the actual task but the lack of memory still gets me.
    Maybe I should have been clearer. What tasks can this do that an AVR, 8051, 68HC11, or Pic can not?
    Heck I didn’t even see any I2C or ADCs on it.

  9. wiml says:

    The propellor design goes to some length to allow you to program with very predictable latency — no jitter, etc., even when you use the inter-cog communication hub. So I’m thinking that the cogs can be used for things like motor control, PWM, bitbanged IO (there’s your SPI, I2C, UART and so forth, since you don’t have to worry about an interrupt coming along and screwing up your timing), waveform synthesis (video out, e.g., but cleverer things are probably possible — you can synthesize video with a plain ol PIC).

    It does kind of seem like a solution looking for a problem. I think the propellor is enough of a departure from the normal way of doing things that it won’t really be clear how useful it is (or isn’t) until people have been using it for a while.

  10. Greg says:

    Call me weird but I am seeing a great lack of creativity in a lot of the responses here.

    This would be great for any glue logic but if you really do want ram, I would chain two together and use one as a memory controller and dedicate one cog on the other for RAM fetch/store operations to said ‘memory controller’. 8-bit between them and there is more than ample bandwidth for a lot of imbedded applications. I/O tight? 4-bit between chip 1 and 2. Need more speed? 16-bit. Be creative! What kind of engineer can’t solve engineering issues?

    1. Micro_Engineer says:

      The Propeller looks “ok” but not quite competitive with off-the-shelf microcontrollers supporting multiple peripherals, especially newer PICs & 8051s.

      Glue logic is a possibility, but then again a multi-core system is kind of overkill for that (plus CPLDs & FPGAs now offer low cost, lower power, non-volatile alternatives).

      I’m guessing the die for this IC was obtained for less R&D costs for Parallax, as competitor’s models offer much more serious hardware.

      I would anticipate a multi-core unit being good for learning about multi-core CPUs, or SOC with RTOS apps, but from an engineering perspective it wouldn’t be my first pick.

      It would be nice if Parallax could show industry success stories using the Propeller…otherwise, well where does it fit???

      Looks like it might be fun to tinker with.